A Mesochronous Network-on-Chip for an FPGA
نویسندگان
چکیده
Networks-on-Chip (NoCs) are a new paradigm for the design of integrated systems. NoCs address design complexity and physical issues in ASIC and FPGA designs. In this paper, we present a scalable, mesochronous NoC architecture for an FPGA. A special hybrid switching scheme has been developed for globally asynchronous locally synchronous (GALS) operation of the whole NoC-based system. The NoC was designed with respect to simplicity and a small hardware footprint.
منابع مشابه
Ina-ocmc 2011
MPSoCs are today frequently designed as the composition of multiple voltage/frequency islands, thus calling for a GALS clocking style. In this context, the on-chip interconnection network can be either inferred as a single and independent clock domain or it can be distributed among core’s domains. This paper targets the former scenario, since it results in the homogeneous speed of the NoC switc...
متن کاملLinköping Studies in Science and Technology
Today’s microprocessors with millions of transistors perform high-complexity computing at multi-gigahertz clock frequencies. The ever-increasing chip size and speed call for new methodologies in clock distribution network. Conventional global synchronization techniques exhibit many drawbacks in the advanced VLSI chips such as high-speed microprocessors. A significant percentage of the total pow...
متن کاملReliability and Performance Evaluation of Fault-aware Routing Methods for Network-on-Chip Architectures (RESEARCH NOTE)
Nowadays, faults and failures are increasing especially in complex systems such as Network-on-Chip (NoC) based Systems-on-a-Chip due to the increasing susceptibility and decreasing feature sizes. On the other hand, fault-tolerant routing algorithms have an evident effect on tolerating permanent faults and improving the reliability of a Network-on-Chip based system. This paper presents reliabili...
متن کاملAsynchronous Bypass Channel Routers
Network-on-Chip (NoC) designs have emerged as a replacement for traditional shared-bus designs for on-chip communications. Typically, these systems require fully balanced clock distribution trees to enable synchronous communication between all nodes on-chip, resulting in higher power consumption. One approach to reduce power consumption is to replace the balanced clock tree with a globally-asyn...
متن کاملHigh bandwidth, Low Latency Global Interconnect
Global interconnects have been identified as a serious limitation to chip scaling, due to their limited bandwidth and large delay. A critical analysis of intrinsic limitations of electrical interconnect indicates that these limitations can be overcome. This basic analysis is presented, together with design constraints. We demonstrate a scheme for this, based on the utilization of upper-level me...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2007